Electrical device with teeth joining layers and method for making the same

ABSTRACT

A multilayer electrical device, such as a printed circuit board, having a tooth structure including a metal layer set in a dielectric. The device includes a base; a conductive layer adjacent to the base; a dielectric material adjacent to conductive layer; a tooth structure including a metal layer set in the dielectric material to join the dielectric material to the metal layer; and wherein the metal layer forms a portion of circuitry in a circuit board having multiple layers of circuitry.

I. CLAIM OF PRIORITY

The present patent application is a continuation of, and incorporates by reference as if fully restated herein, U.S. patent application Ser. No. 14/048,592, filed Oct. 8, 2013, pending. U.S. Ser. No. 14/048,592 is a continuation of and incorporates by reference as if fully restated herein, U.S. Ser. No. 13/632,742, filed Oct. 1, 2012, issuing on Nov. 12, 2013, as U.S. Pat. No. 8,581,105. U.S. Ser. No. 13/632,742 is a continuation of and incorporates by reference as if fully restated herein, U.S. patent application Ser. No. 12/363,501, filed Jan. 30, 2009, issuing on Oct. 2, 2012, as U.S. Pat. No. 8,278,560. Ser. No. 12/363,501 is a continuation of and incorporates by reference as if fully restated herein, Ser. No. 10/790,363, filed Mar. 1, 2004, issuing Mar. 10, 2009, as U.S. Pat. No. 7,501,582. Ser. No. 10/790,363 is a continuation of and incorporates by reference as if fully restated herein, Ser. No. 09/694,099, filed Oct. 20, 2000, issuing on Mar. 2, 2004, as U.S. Pat. No. 6,700,069. Ser. No. 09/694,099 is a continuation of and incorporates by reference as if fully restated herein, Ser. No. 08/905,619, filed Aug. 4, 1997, issuing on Nov. 7, 2000, as U.S. Pat. No. 6,141,870. The present patent application incorporates by reference all of the patent applications and patents listed above.

II. FIELD OF THE INVENTION

The present invention is directed to methods for making or manufacturing an electrical device, and the process, composition, and product thereof. More particularly, the present invention involves such multilayer electrical devices as circuit boards constructed by joining a dielectric material to a subsequently applied conductive material. Still more particularly, the present invention involves an electrical device having a substrate or base, an applied dielectric material thereon, which in turn has a thin conductive coating thereon, and a conductive layer formed upon the conductive coating, the conductive layer being joined to the applied dielectric material in an improved manner.

III. BACKGROUND OF THE INVENTION

Multilayer electrical devices—those made from layering a dielectric material and a conductive material on a base—suffer from delamination, blistering, and other reliability problems. This is particularly true when the laminates are subjected to thermal stress.

Known attempts to solve these problems seem to have focused on physical or chemical roughening, particularly of the base or substrate. See for example, U.S. Pat. No. 4,948,707. Although oxide-related chemical roughening processes have been used, an emphasis on physical roughening may reflect the use of materials that are relatively chemically resistant. Both physical and chemical roughening approaches have improved adherence to the base.

However, the extent to which this adherence can be increased by roughening has its limits. And despite a long standing recognition of delamination, blistering, and reliability problems, and the attempts to find a solution, these problems have been persistent in electrical devices made of layered materials.

IV. SUMMARY OF THE INVENTION

The inventors herein have observed that the general problem of poor adherence between the laminates or layers can be addressed by forming a unique surface structure, which is particularly suitable for joining the dielectric material to the conductive coating and conductive layer. The surface structure is comprised of teeth that are preferably angled or hooked like fangs or canine teeth to enable one layer to mechanically grip a second layer.

In comparison with the above-mentioned roughening techniques of the prior art, it is believed that a surface of the teeth is an improvement in that there is an increase in surface area. However, it is still better to use teeth that are fang-shaped to enable a mechanical grip that functions in a different manner than adherence by means of increased surface area. By using the fanged, angled, canine, or otherwise hooked teeth (in addition to increased surface area), there is a multidirectional, three dimensional interlacing or overlapping of layers. For example, in joining the dielectric material to the conductive coating and metal layer, the conductive coating and metal layer is actually burrowed in and under the dielectric material and vice versa. Thus, separating them not only involves breaking the surface area adherence, but also involves destroying the integrity of at least one of the layers by ripping the teeth, the layer pierced by them, or both.

Further, it has been found preferable to have numerous teeth sized and shaped so that they are not too large or too small. If the teeth are too small, wide, straight, and shallow, then the surface resembles the roughened surface of prior art techniques, vaguely analogous to a surface of molar teeth, and the adherence is not much better than that achieved by known prior art roughening techniques.

However, if the teeth are too large, deep, and fanged or hook-shaped, the teeth undercut the surface to such an extent that the strength of the dielectric material surface is weakened. As a result, adherence is decreased over the preferred embodiment.

Not too great and not too slight, the right sized and shaped teeth, set in a fanged orientation and with sufficient frequency, have been found to be the best structure. If the correct balance of these critically important factors is created, the result is a greatly improved circuit board or other such electrical device.

It is theorized by the inventors that the best methods for producing the teeth is to use non-homogeneous materials and/or techniques. For example, a dielectric material can have a non-homogeneous composition or thickness to bring about an uneven chemical resistance, such that slowed and/or repeated etching will form teeth instead of a uniform etch.

V. BRIEF DESCRIPTION OF THE DRAWINGS

The file of this patent contains at least one drawing executed in color. Copies of this patent with the color drawing(s) will be provided by the Patent and Trademark Office upon request and payment of the necessary fee.

FIG. 1 is an illustration of a conductive coating and metal layer applied dielectric material with a desirable tooth structure;

FIG. 2 is an illustration of a prior art conductive coating and metal layer on the applied dielectric material with the surface produced by roughening processes;

FIG. 3 is an illustration of a double sided printed circuit board without plated through holes;

FIG. 4 is an illustration of a multilayer printed circuit board with plated through holes, filled or unfilled with conductive or nonconductive material;

FIG. 5 is an illustration of a multilayer printed circuit board without plated through holes;

FIG. 6 is an illustration of a multilayer printed circuit board having more than two layers with plated through holes filled or unfilled with conductive or nonconductive material;

FIG. 7 is an illustration of any of the foregoing printed circuit boards after applying a dielectric material thereon;

FIG. 8 is an illustration of the multilayer printed circuit board of FIG. 7 after forming micro vias;

FIG. 9 is an illustration of the multilayer printed circuit board of FIG. 7 after opening the through holes and after etching the applied dielectric material to produce the teeth illustrated in FIG. 1;

FIG. 10 is an illustration of the multilayer printed circuit board of FIG. 9 after application of a conductive coating to fill in around the teeth and connect micro via holes and the through holes; and

FIG. 11 is an illustration of the multilayer printed circuit board of FIG. 10 after plating the conductive coating to form a metal layer and complete forming circuitry.

VI. DETAILED DESCRIPTION OF THE DRAWINGS

FIG. 1 is an illustration of a conductive coating and metal layer on the applied dielectric material with a desirable tooth structure. In contrast, FIG. 2 is an illustration of a prior art conductive coating and metal layer on the applied dielectric material with the surface produced by roughening processes. In both FIGS. 1 and 2, show a dielectric material and a combination of a thin conductive coating and metal later. Compare FIG. 1 and FIG. 2, and note particularly the size, shape, frequency, and depth of the teeth in FIG. 1 with the surface produced by roughening in FIG. 2.

A way of articulating this “teeth” concept is to view each tooth as being made of one layer and set in a second layer. However, the perspective is arbitrary, and one could equally view each tooth as made of the second layer set in the first. It could also be said that the layers join in a saw-toothed manner, i.e., teeth made of both materials in an interlocking bite. In any case, however, there are teeth, and for the sake of consistency, this specification will adopt the convention of referring to the teeth as being made of the conductive coating and metal layer set in the dielectric material.

A further way of articulating the “teeth” concept is to view each tooth as being substantially triangular in shape, with the base of the triangle being defined by a plane of the applied dielectric material before it is etched, or more precisely by the exterior surface thereof. The invention can be carried by forming cavities in the applied dielectric material 6 for receiving the teeth, and then forming the teeth from the conductive coating and metal layer formed thereon. Generally, the teeth can be of any triangular shape (e.g., equilateral, isosceles, scalene, right, obtuse, or any combination thereof). Preferably, though, the teeth are obtuse so as to hook or angle under the exterior surface of the applied dielectric material.

The use of any shape of teeth increases the surface area where the conductive coating is on the applied dielectric material. However, the preferred embodiment utilizes a surface of obtuse, canine, or fang-shaped teeth to help the conductive coating and metal layer hook under the exterior surface of the applied dielectric material to mechanically grip the applied dielectric material. The obtuse, canine, or fang-shaped teeth are in contrast to the shallower, more rounded surface typically produced by known roughening techniques. Note in FIG. 2 that roughing techniques can produce some occasional gouging, but nothing on the order of the present invention.

As to size of the teeth, as mentioned above, it is preferable that the teeth be within a certain size range. The optimal size range for obtuse, canine, or hook-shaped teeth involves a balance between maximizing surface area and mechanical grip, but not undercutting the surface of the applied dielectric material 8 to such an extent as to weaken it. Accordingly, the teeth should be sized at least 1 tenth of a mil deep. Better is at least 1.25 tenths of a mil deep, and even better is at least 1.5 tenths of a mil deep. However, 1.75 tenths of a mil is acceptable, and about 2 tenths of a mil is reaching the limit.

As to frequency, the teeth should be quite frequent in number; at least about 5,000 teeth per linear inch, and preferably at least about 10,000 teeth per linear inch; and even better is at least about 15,000 teeth per linear inch.

As to surface area, there should be at least about 25,000 teeth per square inch, better still is essentially at least about 100,000 per square inch, and preferably at least about per 200,000 per square inch, or even greater.

It should be recognized that the teeth generally are not formed to a precise dimension. As shown in FIG. 1, some of the teeth are somewhat differently sized, angled, and proportioned. Thus, a representative sample of the electrical device should have teeth in about these ranges. Having at least about 20% of the teeth in one or more of these ranges, and preferably at least 50%, is a preferred balance of mechanical grip without a weakening the integrity of the layering, particularly in combination.

As illustrated in FIGS. 3-11, there is an electrical device, such as a printed circuit board 2 having a base 4. The base 4 has a conductive layer 6 thereon. A dielectric material 8 is applied on the conductive layer 6, and a conductive coating 10 (such as a thin coating of palladium) is deposited on the dielectric material 8. Metal layer 12 is formed on the conductive coating 10.

FIG. 3 illustrates one of the many ways to begin the process of forming the teeth in accordance with the present invention. A first step (step 1), includes providing a base 4 for constructing an electrical device, such as a printed circuit board 2. FIG. 3 illustrates one such construction, namely a base 4 for constructing a multilayer printed circuit board 2, the base 4 having any positive number of layers or laminates, for example the two layers shown in FIGS. 3 and 4, or more than two layers as illustrated in FIGS. 5 and 6, etc. One configuration or another is not significant, except that multiple layers provide a better medium for constructing circuitry of increased complexity or density. FIGS. 3-6 illustrate an embodiment in which the conductive layer 6 is on at least an upper side, and preferably also on a lower side of the base 4.

As may be needed for a particular circuitry design, FIG. 4 illustrates that the electrical device can be further manipulated, for example, by forming through holes 12 by mechanical drilling, laser drilling, punching, or the like. The plated through holes 12 are shown in FIGS. 4 and 6 as filled or unfilled with a conductive or a nonconductive material.

FIG. 5 illustrates a configuration for the multilayer printed circuit board 2 with base 4 having more than two layers or laminates, the conductive layers 6 located there between.

FIG. 6 shows the multilayer printed circuit board 2 after forming, plating, and if needed, filling the through holes 12 in the manner of FIG. 4.

To summarize, step 1 of the process includes providing a base 4 for forming an electrical device such as a printed circuit board 2, wherein the base 4 can be formed to have one or more layers or laminates. At least one conductive layer 6 is on the base 4. The base 4 can be double sided with the conductive layer 6 being located outside the base 4 and between the layers or laminates.

The printed circuit board 2 can be further prepared, as may be desirable for a particular circuitry design, by forming open through holes 12 and plating and if needed, filling the through holes 12 to electrically connect to that portion of the conductive layer 6 appropriate for whatever circuitry design is being constructed, e.g., each side of a double sided circuit board 2. In other words, step 1 involves providing one of the configurations described in FIGS. 3-6.

Step 2 includes preparing an outer-most surface of the conductive layer 6 for any of the above-mentioned configurations. The step of preparing is carried out to enable adherence, e.g., of the applied dielectric material 8 to the conductive layer 6, preferably in a manner that utilizes a respective tooth structure. The step of preparing can be carried out, for example, by using an oxide or an oxide replacement process to treat the conductive layer 6 to such an extent that the teeth (or cavities for teeth) are formed.

As to using an oxide process, a copper oxide can be chemically deposited on a copper surface to produce a tooth-like structure on the surface of the copper. This process is carried out to prepare the copper surface prior to applying another layer of material, thereby providing increased bond strength between the two materials.

As to using an oxide replacement process to form a tooth structure, a micro etch on the surface of the copper is followed by a coating of an adhesion promoter to enhance a bond between copper and the dielectric material 8. For example, Alpha Metals, Inc. offers a PC-7023 product which is suitable for an oxide replacement process.

Step 3 includes applying the dielectric material 8 to the outermost surface of the conductive layer 10 (and the base 4 if appropriate for the circuitry or electrical device at issue) prepared in accordance with the step 2. The dielectric material 8 can be applied by as a (dry) film, a (liquid) curtain coating, a (liquid) roller coating, or an analogous application or bonding technique. FIG. 7, in comparison with FIGS. 3-6, illustrates the dielectric material 8 on the outermost surface(s) of the conductive layer 4 (and the base 2).

Step 4 includes preparing the applied dielectric material 8 for receipt of a conductive coating 10, which to exemplify, is detailed more particularly below. Generally, though, the preparing step 4 can include exposing, developing, and curing the applied dielectric material 8 to form patterns for further construction of the circuitry, including such features as constructing a via or photo via 14, for optionally filling by conductive or non-conductive materials, e.g., screened, roller coated, etc. Compare FIGS. 6 and 7.

Step 5 includes forming open through holes 16 as shown in FIG. 9. As indicated above with regard to filled through holes 12, the open through holes 16 can be formed by such methods as drilling, boring, punching, and the like.

Step 6, as discussed subsequently in greater detail, involves the etching cavities, veins, openings, or gaps in the applied dielectric material 8, or more particularly an outermost surface thereof, to accommodate the teeth. One technique for forming the teeth is somewhat similar to what has been known as the swell and etch or desmear process, except that contrary to all known teachings in the prior art, in effect, a “double desmear process” is utilized. That is, not merely increasing the times and temperatures and other parameters for the desmear process, but instead completing the process a first time, and then completing the process a second time. Consider using the following Shipley products for the double desmear process: CIRCUPOSIT MLB conditioner 211, promoter 213B, and neutralizer 216. Non-homogeneous materials and/or processes seem to be determinative.

Step 7 includes applying a conductive coating 10 to the cavities in the applied dielectric material 8. The conductive coating 10 is also applied to the photo-defined via holes 14 and the open through holes 16. Techniques for applying the conductive coating 10 include a direct plate process or an electroless copper process. To carry out the present invention, it is preferable to use a palladium-based direct plate process or other non-electroless process. In this regard, a Crimson product of Shipley is suitable, though the desmear process as disclosed herein is contrary to the manufacturer's specifications, i.e., a “double desmear process,” rather than the single desmear process of the known prior art. Compare FIGS. 1, 2, and 9.

Step 8 includes forming a metal layer 18 on the conductive coating 10, by such metal deposition techniques as electrolytic or non-electrolytic plating, to form the tooth structure and teeth as discussed above. The metal layer 18 and conductive coating 10 collectively form circuitry on the outermost surface of the applied dielectric material 8, which can connect to whatever portion of conductive layer 6 as may be needed for a particular design, preferably by making at least one connection through a micro via. See FIG. 10. A direct plate process, followed as needed by say a semi-additive or fully additive pattern plating process, is recommended.

A direct plate process is a replacement for traditional electroless copper plating of non-conductive surfaces. Direct plate processes apply a very thin conductive coating (e.g., using palladium or graphite) to the non-conductive surface, thus enabling electroplating of copper or other conductive material onto the previously non-conductive surface. Thus, “direct plate” is used to describe directly plating onto a non-conductive surface without first requiring a non electrolytic (electroless) plating process.

A semi-additive plating process involves first electroplating a thin conductive layer onto the total non-conductive surface, before applying a photoresist and subsequently pattern plating the required circuitry. For semi-additive plating, the thin conductive layer must be removed (etched) from the non-conductive surface. For fully additive plating, photoresist is applied directly on the non-conductive surface, followed by pattern plating the required circuitry (after applying the thin conductive coating in the direct plate process). That is, the fully additive plating forms only the required circuitry and requires no etching.

It should be recognized that the present invention can optionally be carried out by initially skipping step 5 (forming the open through holes 16) during initial “sets” of the foregoing steps, i.e., completing steps 6 and 7; then repeating steps 2 through 8, again skipping step 5 each time until the last set of steps, as required to form the electrical device or circuitry of interest. This will produce an electrical device with a second tooth structure that is not set in the first layer of dielectric material 8, and indeed the idea of using a toothed structure is not limited to any one layer and is best employed in holding multiple layers together. Step 5 can be carried out after the desired layers have been formed.

Turning now more particularly to the process for forming the teeth and the cavities for the teeth, the present invention can be carried out by a new use of a Ciba-Geigy product known as Probelec XB 7081 as a photoimagable dielectric material 8. Generally, and in accordance with its specification sheet, Probelec XB 7081 is a single component, 100% epoxy photodielectric material specially developed for Sequential Build Up (SBU) of multilayer boards.

Probelec XB7081 is a negative working, high resolution liquid photo-imageable (LPI) material which allows mass-forming of micro vias for fabrication of high-density interconnects (HDI). Compatible with conventional plating and circuitization techniques, Probelec XB 7081 also provides outstanding electrical and physical properties for most circuit board applications, and is compatible with most circuit board substrate materials.

Probelec XB 7081 is specially developed to act as a dielectric between circuit layers in fabrication of blind and buried micro via MLBS. The high resolution photo dielectric allows mass forming of micro vias for the construction of high density interconnects. Probelec XB 7081 has wide process latitudes, excellent handling characteristics, and is known as self-leveling and having an adjustable dry thickness of 1-3 mils. Probelec XB 7081 has a high resolution capability of 1-2 mil micro vias, and is known for chemical resistance, even for additive plating; there are excellent electrical and physical properties and a UL 94V-0 rating. Probelec is specified to demonstrate more than a 6 lb/in peel strength. By application of this invention this peel strength should be significantly increased due to the formation of the teeth. Accordingly the peel strength produced in accordance with the present invention is greater than the peal strength produced by the desmear process of the prior art, i.e., a single pass desmear process. For example, if a prior art desmear process is used to produce a 6 lb/in average peel strength, the present invention may produce an average peel strength on the order of 10 lb/in or more.

As to the general properties of Probelec XB 7081, there is a storage stability (1-component system) for more than 6 months at 25° C.; the pot life in a coater machine is more than 1 week; the hold time of the coating is more than 1 week (dark or exposed) and more than 1 day in yellow light.

When using Probelec XB 7081 to carry out the above-mentioned step 3 of applying a coating of the dielectric material, there is a pre-cleaning sub-step A. Pre-cleaning should be carried out in chemical, mechanical brushing, or pumice spray units. Extra precaution is needed to ensure that the pre-cleaning equipment and chemistry is not contaminated by materials from previous processing steps. Contrary to Ciba specifications, it is preferred to use an oxide or oxide replacement to prepare the surface prior to applying a coating of the dielectric. Hold times after pre-cleaning should be minimized to avoid oxidation of copper surfaces. In all coating applications, pre-cleaned substrates should be free of particles. Additional cleaning steps, e.g., with detergents, may be required to remove organic residues.

Next there is a coating sub-step B. Probelec XB7081 seems to have been primarily designed for curtain coating and is delivered with a solid content of 58%. Substrates should be heated to about 40° C. prior to coating to ensure all residual moisture is removed and to prepare substrate for curtain coating. For initial charging of a coater machine, Probelec XB 7081 needs to be premixed with about 15% of PMA (PMA is 1-methoxy-2-propyl acetate) to ensure proper viscosity. The additional PMA thins the coating down to about 50% solids.

The resin temperature should be 25±1° C., with a conveyor speed of 90 m/min. The viscosity is at 25° C., DIN AK4 cup at 60 sec. (400 cps), with a coater gap width of 500 mm. The wet weight is 7.5-1 0.0 gms/600 CM sq. and 11.6-1 5.5 gms/ft sq. The dry thickness is 45-60 mm.

Next is a flash dry sub-step C. Coated panels must be held in a horizontal position under dust-free conditions to air dry. At this stage, minimal air flow is recommended. The drying time is 12-18 min. at a drying temperature of 30-40° C.

Next is a final dry sub-step D. After flash air drying, final drying at an elevated temperature is needed to achieve better than 95% removal of solvents for tack-free handling. This can be accomplished in batch or conveyorized tunnel ovens, as follows:

Tunnel Oven Batch Oven Drying Temperature: 130-140° C. 90° C. Drying Time: 2-3 minutes 30 minutes After cooling, the panels can have a second side coating (sub-steps A through D) if appropriate for the circuit design, and then for an exposure sub-step E.

In the exposure sub-step E, catalyst for cross linking of epoxy resin is generated. The main spectral sensitivity of Probelec XB 7081 is in the range of 350-420 nm. Conventional exposure units, collimated or non-collimated, with peak spectral emission of 365 nm are recommended. Both diazo and silver halide films are suitable as working phototools. Good artwork to coating contact is essential for consistent micro via reproduction. The exposure energy is 1200-1600 mJ/cm sq. and the exposure time (7 kW) is 30-40 seconds. The Stouffer Step (21 scale) is 5-7.

Next is a thermal bump step F. Thermal bump provides the energy for crosslinking the catalyzed epoxy resin. This process can be done in convection batch or conveyorized tunnel ovens. For a batch oven, 110° C. for 60 min. is appropriate, and for a conveyorized tunnel oven, 130° C. for 10-20 min. is appropriate.

Next is a developing sub-step G. The unexposed areas of Probelec XB7081 are developed away in continuous spray developing machines. Various models with different processing capacities are available for this purpose. A Ciba-Geigy product DY 950 (Gamma-Butyrolactone (GBL)) developer is recommended for processing Probelec XB7081. This developer is a halogen-free, high-boiling organic solvent suitable for on-site distillation or recycling. Probimer 450/470 spray developing equipment is specially designed for use with this developer solution. The temperature is 20±2° C., and the spray pressure is 2-4 bar. The speed for Probimer 450 is 2-3 m/min; for Probimer 470, 3-4 m/min.

Next is a final cure sub-step H. Final thermal curing is needed to impart good mechanical, chemical, and electrical properties to the dielectric film. The thermal curing can take place in batch or conveyorized tunnel ovens. The thermal curing temperature is 150° C., with a thermal curing time of 60 minutes.

Next can come the step 5 of further preparing, for example, by forming through holes 16. If plated through holes 16 (PTH's) are needed for interconnecting layers to the bottom or back side of the printed circuit board 2, drilling should of course be done before plating. This allows the plating of the surface together with the through holes 16. Plating and such post-processing of the photoimagable dielectric material 8 is dependent on particular process preferences. Probelec XB7081 is compatible with panel-plate, pattern-plate or additive plating.

The following process sub-steps of the above-mentioned step 6 describe a generic sequence for a desmear process to form cavities in the dielectric. Although Probelec XB7081 apparently was intended for use in the common desmear (swell and etch) process as used in conventional plated through hole plating lines, Probelec XB7081 can alternatively be used in carrying out the present invention. For example, the present invention differs from the common desmear process in that sub-steps in the desmear process are repeated as a way of forming the teeth. Sub-step A, swelling the dielectric material 8, can be carried out with butyl diglycol/sodium hydroxide/water 80° C. for 3-5 minutes. Sub-step B is rinsing the dielectric material 8 in deionized water at room temperature for 4 minutes. Sub-step C is etching the dielectric material 8, which can be carried out using potassium permanganate/sodium hydroxide/water 80° C., 6-10 minutes. Sub-step D is rinsing the dielectric material 8 in deionized water at room temperature for 4 minutes. Sub-step D includes a further rinsing of the dielectric material 8 in deionized water at room temperature for 4 minutes. Sub-step E is neutralizing the dielectric material 8 in sulfuric peroxide (1.5%) for 3 to 5 minutes. Finally step F is rinsing the dielectric material 8 in deionized water at room temperature for 4 minutes.

In stark contrast with the etch and swell process of the known prior art, however, a second pass through the process (sub-steps A through F) is used. The second pass seems to make use of non-homogenaities in bringing about a formation of the teeth. Thus, unlike the prior swell and etch chemical roughening process, which produces a surface characterized by a surface gloss measurement at an angle of 60° which is between 15 and 45%, the present invention has less gloss (<10%).

Turn now in greater detail to the step 7 of applying the conductive coating 10 for subsequent deposition of the metal layer 18 by, say, plating. Good results can be achieved with a flash plate of 0.7-1.0 mm (30-40 micro inches). The flash plate is followed by baking at 130-150° C., for 2 hours.

For pattern plating, plating resist can be applied after baking. Depositing the metal layer 18 by electroplating can be carried out such that there is 10-25 mm (0.4-1.0 mil.).

While a particular embodiment of the present invention has been disclosed, it is to be understood that various different modifications are possible and are within the true spirit of the invention, the scope of which is to be determined with reference to the claims set forth below. There is no intention, therefore, to limit the invention to the exact disclosure presented herein as a teaching of one embodiment of the invention. 

1. (canceled)
 2. A process of making an electrical device, the process comprising: constructing an electrical device comprising circuitry and a dielectric material, the circuitry comprising means for joining the circuitry to the dielectric material, the means for joining configured by the dielectric material being an epoxy dielectric material delivered with solid content sufficient that etching the epoxy of the dielectric material forms a roughened surface comprising cavities disposed in and underneath some of the dielectric material, and sufficient that the etching of the epoxy uses non-homogeneity with the solid content to bring about formation of the cavities, wherein the means for joining is located within the cavities of the electrical device.
 3. A process of making an electrical device, the process comprising: constructing an electrical device comprising a dielectric material and circuitry interlocked to the dielectric material by teeth shaped by the dielectric material being an epoxy dielectric material delivered with solid content sufficient that etching the epoxy of the dielectric material forms a roughened surface comprising cavities disposed in and underneath some of the dielectric material, and sufficient that the etching of the epoxy uses non-homogeneity with the solid content to bring about formation of the roughened surface, wherein the shaped teeth of the circuitry are located within the cavities of the electrical device.
 4. A process of making an article of manufacture, the process comprising: implementing a circuit design for an electrical device with circuitry comprising filled cavities in an epoxy dielectric material disposed in combination with the circuitry and coupled in a configuration where the epoxy dielectric material comprises a roughened surface comprising said cavities which are located in and underneath an initial surface of the epoxy dielectric material that is delivered with solid content being non-homogeneous to bring about formation of the cavities by etching of the epoxy.
 5. A process of making an article of manufacture, the process comprising: implementing a circuit design for an electrical device with circuitry comprising means for interlocking circuitry with a dielectric material, the means for interlocking configured to fill cavities in an epoxy dielectric material disposed in combination with the circuitry and coupled with the circuitry in a configuration where the dielectric material comprises a roughened surface comprising the cavities located in and underneath an initial surface of the dielectric material that is delivered with solid content being non-homogeneous and configured to bring about formation of the roughened surface by etching of the epoxy.
 6. An article of manufacture, the article comprising: an epoxy dielectric material delivered with solid content sufficient that etching the epoxy forms a roughened surface comprising cavities located in and underneath an initial surface of the dielectric material, and sufficient that the etching of the epoxy uses non-homogeneity with the solid content to shape the cavities, and thereby shape a conductive material built up in the cavities, in an electrical device which includes circuitry comprising the shaped conductive material.
 7. The process of claim 2, wherein the electrical device is a circuit board.
 8. The process of claim 3, wherein the electrical device is a circuit board.
 9. The process of claim 4, wherein the electrical device is a circuit board.
 10. The process of claim 5, wherein the electrical device is a circuit board.
 11. The article of claim 6, wherein the electrical device is a circuit board.
 12. The process of claim 2, wherein: the etching includes a first etching and a second etching, a sample of the means for joining the circuitry to the dielectric material comprises least 50% of teeth set in the cavities at 5,000 per linear inch, and the teeth are disposed sufficiently that separation of the dielectric material from the means for joining the circuitry to the dielectric material requires destroying integrity of the means for joining and the dielectric material.
 13. The process of claim 2, wherein: the etching includes a first etching and a second etching, a sample of the means for joining the circuitry to the dielectric material comprises at least 20% of teeth set in the cavities at 5,000 per linear inch, and the teeth are disposed sufficiently that separation of the dielectric material from the means for joining the circuitry to the dielectric material requires destroying integrity of the means for joining and the dielectric material.
 14. The process of claim 2, wherein: the etching includes a first etching and a second etching, a sample of the means for joining the circuitry to the dielectric material comprises at least 50% of teeth set in the cavities at 10,000 per linear inch, and the teeth are disposed sufficiently that separation of the dielectric material from the means for joining the circuitry to the dielectric material requires destroying integrity of the means for joining and the dielectric material.
 15. The process of claim 2, wherein: the etching includes a first etching and a second etching, a sample of the means for joining the circuitry to the dielectric material comprises at least 20% of teeth set in the cavities at 10,000 per linear inch, and the teeth are disposed sufficiently that separation of the dielectric material from the means for joining the circuitry to the dielectric material requires destroying integrity of the means for joining and the dielectric material.
 16. The process of claim 2, wherein: the etching includes a first etching and a second etching, a sample of the means for joining the circuitry to the dielectric material comprises at least 50% of teeth set in the cavities at 15,000 per linear inch, and the teeth are disposed sufficiently that separation of the dielectric material from the means for joining the circuitry to the dielectric material requires destroying integrity of the means for joining and the dielectric material.
 17. The process of claim 2, wherein: the etching includes a first etching and a second etching, a sample of the means for joining the circuitry to the dielectric material comprises at least 20% of teeth set in the cavities at 15,000 per linear inch, and the teeth are disposed sufficiently that separation of the dielectric material from the means for joining the circuitry to the dielectric material requires destroying integrity of the means for joining and the dielectric material.
 18. The process of claim 3, wherein: the etching includes a first etching and a second etching, a sample of the means for joining the circuitry to the dielectric material comprises at 50% of teeth set in the cavities at 5,000 per linear inch, and the teeth are disposed sufficiently that separation of the dielectric material from the means for joining the circuitry to the dielectric material requires destroying integrity of the dielectric material.
 19. The process of claim 3, wherein: the etching includes a first etching and a second etching, a sample of the circuitry comprises least 20% of the teeth set in the cavities at 5,000 per linear inch, and the teeth are disposed sufficiently that separation of the dielectric material from the circuitry requires destroying integrity of the dielectric material.
 20. The process of claim 3, wherein: the etching includes a first etching and a second etching, a sample of the circuitry comprises least 50% of the teeth set in the cavities at 10,000 per linear inch, and the teeth are disposed sufficiently that separation of the dielectric material from the circuitry requires destroying integrity of the dielectric material.
 21. The process of claim 3, wherein: the etching includes a first etching and a second etching, a sample of the circuitry comprises least 20% of the teeth set in the cavities at 10,000 per linear inch, and the teeth are disposed sufficiently that separation of the dielectric material from the circuitry requires destroying integrity of the dielectric material.
 22. The process of claim 3, wherein: the etching includes a first etching and a second etching, a sample of the circuitry comprises least 50% of the teeth set in the cavities at 15,000 per linear inch, and the teeth are disposed sufficiently that separation of the dielectric material from the circuitry requires destroying integrity of the dielectric material.
 23. The process of claim 3, wherein: the etching includes a first etching and a second etching, a sample of the circuitry comprises least 20% of the teeth set in the cavities at 15,000 per linear inch, and the teeth are disposed sufficiently that separation of the dielectric material from the circuitry requires destroying integrity of the dielectric material.
 24. The process of claim 4, wherein: the etching includes a first etching and a second etching, a sample of the circuitry comprises least 50% of teeth set in the cavities at 5,000 per linear inch, and the teeth are disposed sufficiently that separation of the dielectric material from the means for joining the circuitry to the dielectric material requires destroying integrity of the circuitry.
 25. The process of claim 4, wherein: the etching includes a first etching and a second etching, a sample of the circuitry comprises least 20% of teeth set in the cavities at 5,000 per linear inch, and the teeth are disposed sufficiently that separation of the dielectric material from the means for joining the circuitry to the dielectric material requires destroying integrity of the circuitry.
 26. The process of claim 4, wherein: the etching includes a first etching and a second etching, a sample of the circuitry comprises least 50% of teeth set in the cavities at 10,000 per linear inch, and the teeth are disposed sufficiently that separation of the dielectric material from the circuitry requires destroying integrity of the circuitry.
 27. The process of claim 4, wherein: the etching includes a first etching and a second etching, a sample of the circuitry comprises least 20% of teeth set in the cavities at 10,000 per linear inch, and the teeth are disposed sufficiently that separation of the dielectric material from the circuitry requires destroying integrity of the circuitry.
 28. The process of claim 4, wherein: the etching includes a first etching and a second etching, a sample of the circuitry comprises least 50% the teeth set in the cavities at 15,000 per linear inch, and the teeth are disposed sufficiently that separation of the dielectric material from the circuitry requires destroying integrity of the circuitry.
 29. The process of claim 4, wherein: the etching includes a first etching and a second etching, a sample of the circuitry comprises least 20% of the teeth set in the cavities at 15,000 per linear inch, and the teeth are disposed sufficiently that separation of the dielectric material from the circuitry requires destroying integrity of the circuitry.
 30. The process of claim 5, wherein: the etching includes a first etching and a second etching, a sample of the means for interlocking the circuitry to the dielectric material comprises least 50% of teeth set in the cavities at 5,000 per linear inch, and the teeth are disposed sufficiently that separation of the dielectric material from the means for interlocking the circuitry to the dielectric material requires destroying integrity of the means for interlocking and the dielectric material.
 31. The process of claim 5, wherein: the etching includes a first etching and a second etching, a sample of the means for interlocking the circuitry to the dielectric material comprises at least 20% of teeth set in the cavities at 5,000 per linear inch, and the teeth are disposed sufficiently that separation of the dielectric material from the means for interlocking the circuitry to the dielectric material requires destroying integrity of the means for interlocking and the dielectric material.
 32. The process of claim 5, wherein: the etching includes a first etching and a second etching, a sample of the means for interlocking the circuitry to the dielectric material comprises at least 50% of teeth set in the cavities at 10,000 per linear inch, and the teeth are disposed sufficiently that separation of the dielectric material from front the means for interlocking the circuitry to the dielectric material requires destroying integrity of the means for interlocking and the dielectric material.
 33. The process of claim 5, wherein: the etching includes a first etching and a second etching, a sample of the means for interlocking the circuitry to the dielectric material comprises at least 20% of teeth set in the cavities at 10,000 per linear inch, and the teeth are disposed sufficiently that separation of the dielectric material from the means for interlocking the circuitry to the dielectric material requires destroying integrity of the means for interlocking and the dielectric material.
 34. The process of claim 5, wherein: the etching includes a first etching and a second etching, a sample of the means for interlocking the circuitry to the dielectric material comprises at least 50% of teeth set in the cavities at 15,000 per linear inch, and the teeth are disposed sufficiently that separation of the dielectric material from the means for interlocking the circuitry to the dielectric material requires destroying integrity of the means for interlocking and the dielectric material.
 35. The process of claim 5, wherein: the etching includes a first etching and a second etching, a sample of the means for interlocking the circuitry to the dielectric material comprises at least 20% of teeth set in the cavities at 15,000 per linear inch, and the teeth are disposed sufficiently that separation of the dielectric material from the means for interlocking the circuitry to the dielectric material requires destroying integrity of the means for interlocking and the dielectric material.
 36. The process of claim 5, wherein: the etching includes a first etching and a second etching, a sample of the means for interlocking the circuitry to the dielectric material comprises least 50% of teeth set in the cavities at 5,000 per linear inch, and the teeth are disposed sufficiently that separation of the dielectric material from the means for interlocking the circuitry to the dielectric material requires destroying integrity of the dielectric material.
 37. The process of claim 5, wherein: the etching includes a first etching and a second etching, a sample of the means for interlocking the circuitry to the dielectric material comprises at least 20% of teeth set in the cavities at 5,000 per linear inch, and the teeth are disposed sufficiently that separation of the dielectric material from the means for interlocking the circuitry to the dielectric material requires destroying integrity of the dielectric material.
 38. The process of claim 5, wherein: the etching includes a first etching and a second etching, a sample of the means for interlocking the circuitry to the dielectric material comprises at least 50% of teeth set in the cavities at 10,000 per linear inch, and the teeth are disposed sufficiently that separation of the dielectric material from the means for interlocking the circuitry to the dielectric material requires destroying integrity of the dielectric material.
 39. The process of claim 5, wherein: the etching includes a first etching and a second etching, a sample of the means for interlocking the circuitry to the dielectric material comprises at least 20% of teeth set in the cavities at 10,000 per linear inch, and the teeth are disposed sufficiently that separation of the dielectric material from the means for interlocking the circuitry to the dielectric material requires destroying integrity of the dielectric material.
 40. The process of claim 5, wherein: the etching includes a first etching and a second etching, a sample of the means for interlocking the circuitry to the dielectric material comprises at least 50% of teeth set in the cavities at 15,000 per linear inch, and the teeth are disposed sufficiently that separation of the dielectric material from the means for interlocking the circuitry to the dielectric material requires destroying integrity of the dielectric material.
 41. The process of claim 5, wherein: the etching includes a first etching and a second etching, a sample of the means for interlocking the circuitry to the dielectric material comprises at least 20% of teeth set in the cavities at 15,000 per linear inch, and the teeth are disposed sufficiently that separation of the dielectric material from the means for interlocking the circuitry to the dielectric material requires destroying integrity of the dielectric material.
 42. The article of claim 6, wherein: the etching includes a first etching and a second etching, a sample of the circuitry of the device comprises at least 20% of the teeth at 5,000 of the teeth per linear inch, formation of the roughened surface does not include physical roughening, and the teeth are shaped sufficiently that separation of the dielectric material from the circuitry requires destroying integrity of both the circuitry and the dielectric material.
 43. The process of claim 2, wherein the etching includes a first etching and a second etching.
 44. The process of claim 3, wherein the etching includes a first etching and a second etching.
 45. The process of claim 4, wherein the etching includes a first etching and a second etching.
 46. The process of claim 5, wherein the etching includes a first etching and a second etching.
 47. The article of claim 6, wherein the etching includes a first etching and a second etching.
 48. A product produced by the process of claim
 2. 49. A product produced by the process of claim
 3. 50. A product produced by the process of claim
 4. 51. A product produced by the process of claim
 5. 52. A product produced by the process of claim
 7. 53. A product produced by the process of claim
 8. 54. A product produced by the process of claim
 9. 55. A product produced by the process of claim
 10. 56. A product produced by the process of claim
 12. 57. A product produced by the process of claim
 13. 58. A product produced by the process of claim
 14. 59. A product produced by the process of claim
 15. 60. A product produced by the process of claim
 16. 61. A product produced by the process of claim
 17. 62. A product produced by the process of claim
 18. 63. A product produced by the process of claim
 19. 64. A product produced by the process of claim
 20. 65. A product produced by the process of claim
 21. 66. A product produced by the process of claim
 22. 67. A product produced by the process of claim
 23. 68. A product produced by the process of claim
 24. 69. A product produced by the process of claim
 25. 70. A product produced by the process of claim
 26. 71. A product produced by the process of claim
 27. 72. A product produced by the process of claim
 28. 73. A product produced by the process of claim
 29. 74. A product produced by the process of claim
 30. 75. A product produced by the process of claim
 31. 76. A product produced by the process of claim
 32. 77. A product produced by the process of claim
 33. 78. A product produced by the process of claim
 34. 79. A product produced by the process of claim
 35. 80. A product produced by the process of claim
 36. 81. A product produced by the process of claim
 37. 82. A product produced by the process of claim
 38. 83. A product produced by the process of claim
 39. 84. A product produced by the process of claim
 40. 85. A product produced by the process of claim
 41. 86. A product produced by the process of claim
 42. 87. A product produced by the process of claim
 44. 88. A product produced by the process of claim
 45. 89. A product produced by the process of claim
 46. 90. A product produced by the process of claim
 47. 91. A product produced by the process of claim
 49. 92. A product produced by the process of claim
 50. 93. A product produced by the process of claim
 51. 94. A product produced by the process of claim
 52. 